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Time
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Topic
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Speaker
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13:00-13:30
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報(bào)到 Registration
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|
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13:30-13:35
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開(kāi)幕詞
Opening
|
林志明，晶心科技總經(jīng)理
Frankwell Lin, President
Andes Technology
|
|
13:35-14:05
|
Keynote
|
包云崗博士，中國(guó)開(kāi)放指令生態(tài)（RISC-V）聯(lián)盟秘書(shū)長(zhǎng)暨中科院計(jì)算所研究員
Dr. Yungang Bao, Professor
Institute of Computing Technology, Chinese
Academy of Sciences
|
|
14:05-14:30
|
RISC-V是領(lǐng)先潮流的芯片主架構(gòu)
RISC-V Leads in CPU Architecture for SoC Design
|
林志明，晶心科技總經(jīng)理
Frankwell Lin, President
Andes Technology
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|
14:30-15:10
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Powering RISC-V SoCs with 1 to 1,000s AndesCores
|
蘇泓萌博士，晶心科技 技術(shù)長(zhǎng)兼執(zhí)行副總經(jīng)理
Dr. Charlie Su, CTO & EVP
Andes Technology
|
|
15:10-15:30
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茶歇Tea Break
|
|
15:30-15:55
|
Fast Start into RISC-V for AIoT with A+ Core |
石佳弘，晶心科技解決方案架構(gòu)工程處副處長(zhǎng)
John Shih, Deputy Director of Solution
Architecture Division
Andes Technology
|
|
15:55-16:25
|
Faraday RISC-V based ASIC Solution for Edge AI
and IoT SoCs
|
Kenneth Lu, Marketing Manager
Faraday智原科技
|
|
16:25-16:55
|
Security Enclave
Based on RISC-V
|
Christopher
Beaver, Field Application Engineer for Embedded Security Products
Silex Insight
|
|
16:55-17:25
|
Making RISC-V The Most Secure Platform |
Cesare Garlati, CEO
Hex Five Security, Inc.
|
|
17:25-
|
Q&A / Lucky Draw
|
|
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